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Hidden /Concurrent Refresh : (Enabled/Disabled )
DRAM must be constantly refreshed . Normally when the DRAM is refreshed the CPU must halt all access to the memory and I/O busses , and puts all of its output and I/O pins in a high-impedance state. The memory is refreshed and control of the bus is returned to the CPU . With hidden refresh the CPU is allowed access to cache memory concurrent to memory refreshes . If a local , I/O, or DMA cycle is activated while a hidden refresh is being performed, wait states are inserted into the access cycle until the refresh is completed. If a hidden refresh is attempted while the memory bus is active, the cycle is allowed to finish and then the hidden refresh is performed. Because cache memory accesses are still allowed under hidden /concurrent refresh and the CPU can still go on with its internal calculations, hidden /concurrent refresh can measurably improve system speed performance . If your system supports hidden /concurrent refresh and your memory is up to it, you should enable this option. If you also have slow refresh on, you might not be able to use this option.

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The first notch is DRAM key position. It represents RFU (reserved future use), registered, and unbuffered (in that order from left to middle to right position).

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Registered (also called buffered) memory modules have a register between the DRAM modules and the system's memory controller.

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Buffered memory is an older term for registered memory.

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